A major Chinese technology company has revealed a new strategy for developing advanced computer chips that could help the nation work around US trade restrictions that have limited access to sophisticated manufacturing equipment.
Huawei introduced an innovative semiconductor design philosophy this week that prioritizes enhancing signal transmission speeds instead of continuing the traditional approach of making transistors progressively smaller. This new method could provide China with an alternative pathway to create state-of-the-art chips despite sanctions that have been in place since 2019.
The restrictions have prevented China from obtaining the most sophisticated extreme ultraviolet lithography machines, which has hampered Chinese chipmakers’ ability to compete with global industry leaders like Taiwan’s TSMC in the race to develop increasingly miniaturized manufacturing processes that enhance chip performance.
The semiconductor field has long followed Moore’s Law, which states that the number of transistors on a microchip approximately doubles every two years. Huawei’s alternative strategy introduces what the company calls the Tau Scaling Law, which focuses on reducing the time required for signals to travel through chips and broader computing systems.
The company’s core innovation, known as LogicFolding, involves organizing logic, analogue and memory circuits in layered, more closely connected configurations. This arrangement could potentially enhance density, efficiency and processing speeds over the coming decade.
Supporters view this approach as a method to continue chip advancement as traditional manufacturing improvements begin to plateau.
“For Huawei, chips face two key constraints. One is inevitable that Moore’s Law will hit a physical ‘wall’ within the next decade,” said He Tingbo, the president of Huawei’s semiconductor business, in comments to China’s People’s Daily this week.
“The other is accidental because of the external restrictions that Huawei encountered this ‘wall’ earlier than its peers,” she added, apparently referring to US sanctions on importing advanced manufacturing equipment.
However, some industry experts argue that minimizing latency has always been a component of semiconductor design and that many of the fundamental concepts resemble existing work in three-dimensional stacking, advanced packaging and system optimization.
“This is a breakthrough for Huawei, but it’s not a threat for TSMC,” Nvidia CEO Jensen Huang told reporters in Taipei on Thursday. “TSMC has been using die stacking and 3D packaging for how long now? Almost 10 years. And so TSMC’s technology is very advanced.”
The semiconductor industry has already adopted advanced packaging technologies that stack chips vertically in the pursuit of building more powerful computing systems. TSMC has led this field with its packaging technology called SoIC, which allows for more tightly integrated diverse chiplets to reduce size and boost performance.
Memory chip manufacturers such as SK Hynix and Samsung Electronics also employ advanced 3D stacking and packaging technologies to create multi-layer memory chips, which are essential components of AI chipsets, while improving power efficiency and performance.
Huawei contends that LogicFolding may surpass commonly used 3D integrated circuit stacking techniques by “very finely and carefully split the critical paths of logic circuits across multiple layers,” according to Liao Heng, chief scientist at Huawei Semiconductor.
However, Bernstein analysts warned in a research note that while stacking multiple chip layers increases transistor density, it also raises power density and creates risks of chip overheating. Production yields and costs will present additional obstacles for widespread adoption, they noted.
Huawei’s own development timeline acknowledges these challenges. The company’s executive said the approach would require new semiconductor design tools adapted to folded chip architectures, along with improved methods for managing heat across devices from smartphones to large AI data centers.
“With the methodology of not optimising the area on a chip level, but on a system level based on time, that will dramatically change the capability requirements for the EDA (electronic design automation) vendors,” said Handel H. Jones, CEO of International Business Strategies, during a panel discussion on Tau Scaling on Tuesday.
Standard electronic design automation software from vendors like Cadence Design Systems and Synopsys serves a vital function in developing blueprints for complex semiconductor devices.
Huawei’s most specific assertions focused on a new Kirin smartphone chip scheduled for release later this year, which would be the first to implement its LogicFolding architecture.
Compared to its previous single-layer design, the new chip would boost power efficiency by 41% and increase the chip’s maximum operating speed by nearly 13%, according to Huawei’s He in a speech on Monday.
These numbers would be substantial if achieved in mass production. However, Huawei did not share production yield data, cost comparisons or a detailed explanation of how the improvements would measure against competing chips manufactured using more advanced process technologies.
“There’s nothing concrete that can be independently verified or benchmarked against other players at the moment,” said Lian Jye Su, chief analyst at tech research firm Omdia.
